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PACVGA100 PAC VGA100 same as SWVGA100 VGA PORT ESD PROTECTED TERMINATION manufactured by SEMICONWELL, The SWVGA-100 acts as a transmission line terminating and ESD protection device. In provides 75 ohms parallel terminations for R,G,B lines and series terminations for the Horizontal and Vertical Sync lines and two monitor ID lines which provide 'Plug and Play' logic signals
VGA PORT ESD PROTECTED TERMINATION SWVGA100
FEATURES APPLICATIONS
7 channel ESD protection ESD protection for VGA (video) port in PCs and notebooks.
15 KV ESD protection (HBM)
8 KV contact, 15 KV air discharge ESD protection per IEC1000-4-2 (Level 4)
Low loading capacitance, 4.5pF typical
SHORT PRODUCT APPLICATION NOTE
The SWVGA-100 acts as a transmission line terminating and ESD protection device. In provides 75 W parallel terminations for R,G,B lines and series terminations for the Horizontal and Vertical Sync lines and two monitor ID lines which provide 'Plug and Play' logic signals. In addition, all interface lines provide level 4 ESD protection per the IEC1000-4-2 contact dischare Specification. The SWVGA100 provides internal pull-up resistors for the two monitor ID lines.
SEMICONDUCTOR-THIN FILM MANUFACTURING PROCESS DESCRIPTION
Integrated passive networks are manufactured using advanced thin film technologies including ultra -stable and self passivating Tantalum Nitride resistors, gold interconnect metallization and reliable MNOS capacitors to achieve excellent uniformity, performance and reliability. Thin film resistor technology is the preferred solution for all applications that require low noise, long term stability and excellent performance at very high frequencies. Semiconwell employs proprietary thin film technologies for deposition of a wide range of sheet resistance films from 1W/sq to 10,000 W/sq. All Semiconwell's products are available in die form and as KGD, known good die and are ideal for high reliability hybrid and multi chip module applications. Besides thin film resistors, Semiconwell integrates capacitors, Schottky diodes, Zener diodes and transistors. Integrated passive and active networks are manufactured using Semiconwell's in house high reliability semiconductor manufacturing processes. All semiconductor devices employ precision doping via ion implantation, silicon nitride junction passivation, platinum silicided contacts and gold interconnect metallization for best performance and reliability. MNOS capacitors and Tantalum Nitride resistors are easily integrated with Schottky diodes to provide complete standard and custom RCD solutions. In die form, these products are ideal for hybrid and multi chip module applications. In packaged form, these products are the best solution where space and weight are a concern.
ABSOLUTE MAXIMUM RATINGS
Reverse voltage VR Continuous IF IFRM for tw<100ms Max Power dissipation
7V 100mA 200 mA (20%duty cycle) 100mW@70°C/channel
Stresses beyond listed absolute maximum ratings may cause permanent damage to the device.
ELECTRICAL CHARACTERISTICS
PARAMETER VALUE UNITS
Diode Foward DC Current (Note 1) 20 mA
Storage temperature -65 to 150 °C
Operating Temperature Range 0 to 70 °C
DC Voltage at any Channel Input VN-0.5 to VP+0.5 V
Operating Supply Voltage (VP-VN) 5.5 V
R/G/B termination resistor (R1) tolerance ±5 %
Series termination resistor (R2) tolerance ±5 %
Monitor ID pull-up resistor (R3) tolerance ±10 %
Diode forward voltage,T=25 °C 0.65(min.) 0.95(max.) V
Diode reverse breakvown voltage, T = 25°C Top Diode (Cathode to VP) Bottom Diode (Anode to VN) 17 25 V V
ESD Protection
Peak discharge voltage at pins 7,9,11 and 14 Human Body Model, Method 3015 (Note 6) -4(min.) +4(max.) kV
Pak discharge voltage at pins 2,3,5,6,10,12,15 In-system (Note 2)Human Body Model, Method 3015 (Note 3,4) -15(min.) +15(max.) kV
Contact discharge per IEC1000-4-2 (note 5) -8(min.) +8(max.) kV
Channel Clamp Voltage @15KV ESD HBM , T=25 °C @ pins 2,3,5,6,10,12,15 (Note 3,4) Positive transients Negative transients VP+13.0 VN-13.0 V V
Channel Leakage Current, T=25 °C 0.1(typ.) 1.0(max.) mA
Channel Input Capacitance (Measured @1 MHz) at pins 2,3,5,6,10,12,15 VP=5V, VN=0V, VINPUT=2.5V 4.5(typ.) 7(max.) pF
Note1. Only one diode conducting at a time. Note.2 From I/O pins to VP or VN anly, VP bypassed to VN with 0.2m F ceramic capacitor. Note 3. Human Body Model per MIL-STD-883, Method 3015, Cdischarge=100 pF, Rdischarge=1.5KW , VP=5V, VN=GND. Note 4. This parameter is guaranteed by characterization. Note 5. Standard IEC1000-4-2 with Cdischarge=150 pF, Rdischarge=330 W , VP=5V, VN=GND. Note 6. These pins are not connected directly to the video connector and therefore are not subjected to direct ESD strikes.
PIN DESCRIPTION
LEAD NAME DESCRIPTION
1, 8, 16 VCC Positive voltage supply pins.
2 RGB1 RGB Video Protection Channel 1. Ties to one of the RGB video lines (for example, the Red signal) between the VGA controller device and the video connector.
3 RGB2 RGB Video Protection Channel 2. Ties to one of the RGB video lines (for example, the Blue signal) between the VGA controller device and the video connector.
4, 13 VSS Ground reference supply pin.
5 RGB3 RGB Video Protection Channel 3. Ties to one of the RGB video lines (for example, the Green signal) between the VGA controller device and the video connector.
6 SYNC1_CONN Sync Signal Output 1. Ties to the video connector side of one of the sync lines (for example the Horizontal Sync signal).
7 SYNC1_CTLR Sync Signal Input 1. Connects to the VGA Controller side of one of the sync lines (for example, the Horizontal Sync signal).
9 SYNC2_CTLR Sync Signal Input 2. Connects to the VGA Controller side of one of the sync lines (for example, the Vertical Sync signal).
10 SYNC2_CONN Sync Signal Output 2. Connects to the video connector side of one of the sync lines (for example, the Vertical Sync signal).
11 DDC1_CTLR DDC Signal Input 1. Connects to the VGA Controller side of one of the DDC signals (for example, the bidirectional DDC_Data serial line).
12 DDC1_CONN DDC Signal Output 1. Connects to the connector side of one of the DDC signals (for example, the bidirectional DDC_Data serial line).
14 DDC2_CTLR DDC Signal Input 2. Connects to the VGA Controller side of one of the DDC signals (for example, the bidirectional DDC_Clk).
15 DDC2_CONN DDC Signal Output 2. Connects to the connector side of one of the DDC signals (forexample, the bidirectional DDC_Clk).
GENERAL DIE INFORMATION
Substrate Thickness (mils) Die size (mils) Bonding pads Backside metal
SiO2 / Silicon 10±2 90 x 60 ±3 4x4 mils, 3mm thick, 99.99% electroplated gold with a TiW barrier Au/Si compatible with eutectic and conductive epoxy die attach.
All Semiconwell products are available in die form for chip and wire hybrid circuits and multi chip modules applications. Typical delivery for standard die products is 3-4 weeks ARO. For Chip Scale Packaged (CSP) devices consult factory for an update on availability of certain products.
DIODES RESISTORS CAPACITORS
Diodes offers basic ESD protection, with low forward voltage and low power dissipation. Diodes are small physically resulting low junction capacitance and low loading capacitance. Resistive material is ultra stable TaN with low TCR <75ppm/°C typical. For Rsq<10W/sq and Rsq>500W/sq, the resistive material is proprietary. Power rating/resistor max 100mW for R<1KW and 25mW for R>1KW. Standard tolerance is ±5%. Silicon nitride dielectric, MNOS capacitors exhibit high stability, low temperature coefficients, low leakage <10nA and high BV>50V.
DIE LAYOUT PACKAGE PIN OUT
Vin=3,4,5,6,11,12,13,14
Vss=die backside
Vss=1,8,9,16
Vdd=2,7,10,15
STANDARD PRODUCTS ORDERING INFORMATION
R1(ohm) R2(ohm) R3(ohm) SOIC-16 QSOP-16 TSSOP-16 BARE DIE-16
75 33 2.2k SWVGA100-16SO SWVGA100-16QS SWVGA100-16TS SWVGA100-16BD
SW PART # QUANTITY SOIC-16 U/P($) QSOP-16 U/P($) TSSOP-16 U/P($) BARE DIE U/P($)
SWVGA100 5,000pc -16SO -16QS -16TS -16BD
SWVGA100 10,000pc -16SO -16QS -16TS -16BD
For products sold as bare tested die or known good die KGD, minimum order is 5000pc. Dice are 100% functional tested, visual inspected and shipped in antistatic waffle packs. For special die level KGD requirements, different packaging or custom configurations, contact sw_sales@semiconwell.com |
| SEMICONWELL
Integrated Passive Networks |
VGA PORT ESD PROTECTED TERMINATION SWVGA-100 |
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| SHORT PRODUCT APPLICATION NOTE |
| The SWVGA-100 acts as a transmission line terminating and ESD protection device. In provides 75 W parallel terminations for R,G,B lines and series terminations for the Horizontal and Vertical Sync lines and two monitor ID lines which provide 'Plug and Play' logic signals. In addition, all interface lines provide level 4 ESD protection per the IEC1000-4-2 contact dischare Specification. The SWVGA100 provides internal pull-up resistors for the two monitor ID lines. |
| SEMICONDUCTOR-THIN FILM MANUFACTURING PROCESS DESCRIPTION |
| Integrated passive networks are manufactured using advanced thin film technologies including ultra -stable and self passivating Tantalum Nitride resistors, gold interconnect metallization and reliable MNOS capacitors to achieve excellent uniformity, performance and reliability. Thin film resistor technology is the preferred solution for all applications that require low noise, long term stability and excellent performance at very high frequencies. Semiconwell employs proprietary thin film technologies for deposition of a wide range of sheet resistance films from 1W/sq to 10,000 W/sq. All Semiconwell's products are available in die form and as KGD, known good die and are ideal for high reliability hybrid and multi chip module applications. Besides thin film resistors, Semiconwell integrates capacitors, Schottky diodes, Zener diodes and transistors. Integrated passive and active networks are manufactured using Semiconwell's in house high reliability semiconductor manufacturing processes. All semiconductor devices employ precision doping via ion implantation, silicon nitride junction passivation, platinum silicided contacts and gold interconnect metallization for best performance and reliability. MNOS capacitors and Tantalum Nitride resistors are easily integrated with Schottky diodes to provide complete standard and custom RCD solutions. In die form, these products are ideal for hybrid and multi chip module applications. In packaged form, these products are the best solution where space and weight are a concern. |
| ABSOLUTE MAXIMUM RATINGS | |||
| Reverse voltage VR | Continuous IF | IFRM for tw<100ms | Max Power dissipation |
| 7V | 100mA | 200 mA (20%duty cycle) | 100mW@70°C/channel |
| Stresses beyond listed absolute maximum ratings may cause permanent damage to the device. |
| ELECTRICAL CHARACTERISTICS | ||
| PARAMETER | VALUE | UNITS |
| Diode Foward DC Current (Note 1) | 20 | mA |
| Storage temperature | -65 to 150 | °C |
| Operating Temperature Range | 0 to 70 | °C |
| DC Voltage at any Channel Input | VN-0.5 to VP+0.5 | V |
| Operating Supply Voltage (VP-VN) | 5.5 | V |
| R/G/B termination resistor (R1) tolerance | ±5 | % |
| Series termination resistor (R2) tolerance | ±5 | % |
| Monitor ID pull-up resistor (R3) tolerance | ±10 | % |
| Diode forward voltage,T=25 °C | 0.65(min.) 0.95(max.) | V |
| Diode reverse breakvown voltage, T = 25°C Top Diode (Cathode to VP) Bottom Diode (Anode to VN) |
17 25 |
V V |
| ESD Protection | ||
| Peak discharge voltage at pins 7,9,11 and 14 Human Body Model, Method 3015 (Note 6) | -4(min.) +4(max.) | kV |
| Pak discharge voltage at pins 2,3,5,6,10,12,15 In-system (Note 2)Human Body Model, Method 3015 (Note 3,4) | -15(min.) +15(max.) | kV |
| Contact discharge per IEC1000-4-2 (note 5) | -8(min.) +8(max.) | kV |
| Channel Clamp Voltage @15KV ESD HBM , T=25 °C @ pins 2,3,5,6,10,12,15 (Note 3,4) Positive transients Negative transients |
VP+13.0 VN-13.0 |
V V |
| Channel Leakage Current, T=25 °C | 0.1(typ.) 1.0(max.) | mA |
| Channel Input Capacitance (Measured @1 MHz) at pins 2,3,5,6,10,12,15 VP=5V, VN=0V, VINPUT=2.5V | 4.5(typ.) 7(max.) | pF |
| Note1. Only one diode conducting at a time. Note.2 From I/O pins to VP or VN anly, VP bypassed to VN with 0.2m F ceramic capacitor. Note 3. Human Body Model per MIL-STD-883, Method 3015, Cdischarge=100 pF, Rdischarge=1.5KW , VP=5V, VN=GND. Note 4. This parameter is guaranteed by characterization. Note 5. Standard IEC1000-4-2 with Cdischarge=150 pF, Rdischarge=330 W , VP=5V, VN=GND. Note 6. These pins are not connected directly to the video connector and therefore are not subjected to direct ESD strikes. |
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| PIN DESCRIPTION | ||
| LEAD | NAME | DESCRIPTION |
| 1, 8, 16 | VCC | Positive voltage supply pins. |
| 2 | RGB1 | RGB Video Protection Channel 1. Ties to one of the RGB video lines (for example, the Red signal) between the VGA controller device and the video connector. |
| 3 | RGB2 | RGB Video Protection Channel 2. Ties to one of the RGB video lines (for example, the Blue signal) between the VGA controller device and the video connector. |
| 4, 13 | VSS | Ground reference supply pin. |
| 5 | RGB3 | RGB Video Protection Channel 3. Ties to one of the RGB video lines (for example, the Green signal) between the VGA controller device and the video connector. |
| 6 | SYNC1_CONN | Sync Signal Output 1. Ties to the video connector side of one of the sync lines (for example the Horizontal Sync signal). |
| 7 | SYNC1_CTLR | Sync Signal Input 1. Connects to the VGA Controller side of one of the sync lines (for example, the Horizontal Sync signal). |
| 9 | SYNC2_CTLR | Sync Signal Input 2. Connects to the VGA Controller side of one of the sync lines (for example, the Vertical Sync signal). |
| 10 | SYNC2_CONN | Sync Signal Output 2. Connects to the video connector side of one of the sync lines (for example, the Vertical Sync signal). |
| 11 | DDC1_CTLR | DDC Signal Input 1. Connects to the VGA Controller side of one of the DDC signals (for example, the bidirectional DDC_Data serial line). |
| 12 | DDC1_CONN | DDC Signal Output 1. Connects to the connector side of one of the DDC signals (for example, the bidirectional DDC_Data serial line). |
| 14 | DDC2_CTLR | DDC Signal Input 2. Connects to the VGA Controller side of one of the DDC signals (for example, the bidirectional DDC_Clk). |
| 15 | DDC2_CONN | DDC Signal Output 2. Connects to the connector side of one of the DDC signals (forexample, the bidirectional DDC_Clk). |
| GENERAL DIE INFORMATION | ||||
| Substrate | Thickness (mils) | Die size (mils) | Bonding pads | Backside metal |
| SiO2 / Silicon | 10±2 | 90 x 60 ±3 | 4x4 mils, 3mm thick, 99.99% electroplated gold with a TiW barrier | Au/Si compatible with eutectic and conductive epoxy die attach. |
| All Semiconwell products are available in die form for chip and wire hybrid circuits and multi chip modules applications. Typical delivery for standard die products is 3-4 weeks ARO. For Chip Scale Packaged (CSP) devices consult factory for an update on availability of certain products. | ||||
| DIODES | RESISTORS | CAPACITORS |
| Diodes offers basic ESD protection, with low forward voltage and low power dissipation. Diodes are small physically resulting low junction capacitance and low loading capacitance. | Resistive material is ultra stable TaN with low TCR <75ppm/°C typical. For Rsq<10W/sq and Rsq>500W/sq, the resistive material is proprietary. Power rating/resistor max 100mW for R<1KW and 25mW for R>1KW. Standard tolerance is ±5%. | Silicon nitride dielectric, MNOS capacitors exhibit high stability, low temperature coefficients, low leakage <10nA and high BV>50V. |
| DIE LAYOUT | PACKAGE PIN OUT |
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| Vin=3,4,5,6,11,12,13,14 | |
| Vss=die backside | |
| Vss=1,8,9,16 | |
| Vdd=2,7,10,15 | |
| STANDARD PRODUCTS ORDERING INFORMATION |
| R1(W) | R2(W) | R3(W) | SOIC-16 | QSOP-16 | TSSOP-16 | BARE DIE-16 |
| 75 | 33 | 2.2k | SWVGA100-16SO | SWVGA100-16QS | SWVGA100-16TS | SWVGA100-16BD |
| SW PART # | QUANTITY | SOIC-16 | U/P($) | QSOP-16 | U/P($) | TSSOP-16 | U/P($) | BARE DIE | U/P($) |
| SWVGA100 | 5,000pc | -16SO | -16QS | -16TS | -16BD | ||||
| SWVGA100 | 10,000pc | -16SO | -16QS | -16TS | -16BD | ||||
| For products sold as bare tested die or known good die KGD, minimum order is 5000pc. Dice are 100% functional tested, visual inspected and shipped in antistatic waffle packs. For special die level KGD requirements, different packaging or custom configurations, contact sw_sales@semiconwell.com | |||||||||
| Delivery for packaged RCD standard products is 6-8 weeks ARO. Certain items may be available from stock. For standard products available from stock, there is a minimum line item order of $250.0. Inventory is periodically updated. For 2500pc or larger orders, all surface mount packaged devices are shipped in tape on reel (T/R). For smaller quantities, it may vary. Samples are available only for customers that have issued firm orders pending qualification of product in a particular application. On line Orders have to be verified, accepted and acknowledged by Semiconwell sales department in writing before, becoming non cancelable binding contracts. |
| Semiconwell guarantees continuous supply and availability of any of it's standard products provided minimum order quantities are met. |
| SEMICONWELL has made every effort to have this information as accurate as possible. However, no responsibility is assumed by SEMICONWELL for its use, nor for any infringements of rights of third parties which may result from its use. SEMICONWELL reserves the right to revise the content or modify its product line without prior notice. SEMICONWELL products are not authorized for and should not be used within support systems which are intended for surgical implants into the body, to support or sustain life, in aircraft, space equipment, submarine, or nuclear facility applications without the specific written consent. |
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