PACVGA105 PAC VGA105 same as SW VGA105 VGA PORT ESD PROTECTED TERMINATION manufactured by Semiconwell, The SWVGA-105 incorporates 7 channels of ESD protection for signal lines commonly found in a VGA port for PCs. ESD protection is implemented with current steering diodes designed to safely handle the high peak surge currents associated with the IEC-1000-4-2 Level-4 ESD Protection Standard (8KV contact discharge) VGA PORT ESD PROTECTED TERMINATION SWVGA-105 FEATURES APPLICATIONS 7 channels of ESD protection designed to meet IEC-1000-4-2 Level-4 ESD requirements (8KV contact discharge) ESD protection for VGA (video) port in PCs and notebooks. Very low loading capacitance from ESD protection diodes, < 5pF typical TTL to CMOS level-translating buffers for the HSYNC and VSYNC lines Three independent supply pins to facilitate operation with sub-micron Graphics Controller ICs High impedance pull-ups (50kW to nominal VAUX for HSYNC & VSYNC inputs Pull-up resistors (1.8KW nominal to VCC ) for DDC_CLK and DDC_DATA lines SHORT PRODUCT APPLICATION NOTE The SWVGA-105 incorporates 7 channels of ESD protection for signal lines commonly found in a VGA port for PCs. ESD protection is implemented with current steering diodes designed to safely handle the high peak surge currents associated with the IEC-1000-4-2 Level-4 ESD Protection Standard (8KV contact discharge). When the channels are subjected to an electrostatic discharge, the ESD current pulse is diverted via the protection diodes into the positive supply rails or ground where they may be safely dissipated. The upper ESD diodes for the R, G & B channels are connected to a separate supply rail (VRGB ) to facilitate interfacing to graphics controller ICs with low voltage supplies. The remaining channels are connected to the main 5V rail (VCC ). The lower diodes for the R, G & B channels are also connected to a dedicated ground pin (GNDA) to minimize crosstalk due to common ground impedance. Two non-inverting buffers are also included in this IC for buffering the HSYNC and VSYNC signals from the graphics controller IC. These buffers will accept TTL input levels and convert them to CMOS output levels that swing between GND and VCC . These drivers have a nominal 60W output impedance to match the characteristic impedance of the HSYNC and VSYNC lines of the video cables typically used.The inputs of these drivers also have high impedance pull-ups (50KW nom.) pulling up to the V rail. In addition, the DDC_CLOCK and DDC_DATA channels have 1.8KW .pull-up resistors pulling these inputs up to the main 5V (VCC ) rail. SEMICONDUCTOR-THIN FILM MANUFACTURING PROCESS DESCRIPTION Integrated passive networks are manufactured using advanced thin film technologies including ultra -stable and self passivating Tantalum Nitride resistors, gold interconnect metallization and reliable MNOS capacitors to achieve excellent uniformity, performance and reliability. Thin film resistor technology is the preferred solution for all applications that require low noise, long term stability and excellent performance at very high frequencies. Semiconwell employs proprietary thin film technologies for deposition of a wide range of sheet resistance films from 1W/sq to 10,000 W/sq. All Semiconwell's products are available in die form and as KGD, known good die and are ideal for high reliability hybrid and multi chip module applications. Besides thin film resistors, Semiconwell integrates capacitors, Schottky diodes, Zener diodes and transistors. Integrated passive and active networks are manufactured using Semiconwell's in house high reliability semiconductor manufacturing processes. All semiconductor devices employ precision doping via ion implantation, silicon nitride junction passivation, platinum silicided contacts and gold interconnect metallization for best performance and reliability. MNOS capacitors and Tantalum Nitride resistors are easily integrated with Schottky diodes to provide complete standard and custom RCD solutions. In die form, these products are ideal for hybrid and multi chip module applications. In packaged form, these products are the best solution where space and weight are a concern. ABSOLUTE MAXIMUM RATINGS Reverse voltage VR Continuous IF IFRM for tw<100ms Max Power dissipation 7V 100mA 200 mA (20%duty cycle) 100mW@70C/channel Stresses beyond listed absolute maximum ratings may cause permanent damage to the device. ABSOLUTE MAXIMUM RATINGS PARAMETER VALUE UNITS VCC Supply Voltage GND-0.5, 6.0 V VRGB Supply Voltage GND-0.5, 6.0 V VAUX Supply Voltage GND-0.5, 6.0 V Diode Forward Current (only one diode conducting at a time) 20 mA DC Voltage at Inputs ,R, G, B GND -0.5, VRGB +0.5 V DC Voltage at Inputs ,HSYNC, VSYNC GND -0.5, VAUX +0.5 V DC Voltage at Inputs ,DDC_CLK, DDC_DATA GND -0.5, VCC +0.5 V Storage Temperature -40 to 150 C Operating Ambient Temperature 0 to 70 C Package Power Dissipation 0.75 W RECOMMENDED OPERATING CONDITIONS PARAMETER VALUE UNITS Main Supply Voltage 4.5(min.) 5.5(max.) V RGB Supply Voltage 1.7(min.) 3.7(max.) V Auxiliary Supply Voltage 2.9(min.) 3.7(max.) V Logic High Input Voltage (Note 1) 2.0(min.) V Logic Low Input Voltage (Note 1) 0.8(max.) V Input Voltage ,RGB 0(min.) VRGB(max.) V Input Voltage ,HSYNC, VSYNC 0(min.) VAUX(max.) V Input Voltage ,DDC_CLK, DDC_DATA 0(min.) VCC(max.) V High Level Output Current (Note 1) -8(max.) mA Low Level Output Current (Note 1) 8(max.) mA Operating Free-Air Temperature 0(min.) 70(max.) C ELECTRICAL CHARACTERISTICS PARAMETER VALUE UNITS Diode Forward Voltage@IF = 10mA 1(max.) V Logic High Output Voltage@IOH = -4mA, VCC = 4.5V 4(min.) V Logic Low Output Voltage@IOL = 4mA, VCC = 4.5V 0.4(max.) V Input Current,R, G, B pins; VRGB = 3.63V; VIN = VRGB or GND 1 mA Input Current,HSYNC, VSYNC pins; VAUX = 3.63V; VIN = VAUX 1 mA Input Current,HSYNC, VSYNC pins; VAUX = 3.63V; VIN = GND -30(min.) -72.5(typ.) -95(max.) mA VCC Supply Current @ V CC = 5.5V; VAUX = VRGB = 2.97V;All inputs and outputs floating 35(typ.) 100(max.) mA VRGB Supply Current @ R, G, B pins at VCC or GND;All other input and output floating 10(max.) mA Input Capacitance,R,G, B (Note 4) 5(typ.) pF Input Capacitance, HSYNC, VSYNC (Note 4) 10(typ.) pF Input Capacitance, DDC_DATA, DDC_CLK (Note 4) 5(typ.) pF Pull-up Resistance DDC_DATA, DDC_CLK 1.62(min.) 1.8(typ.) 1.98(max.) kW ESD Withstand Voltage, @ VCC = 5V; VRGB = 3.3V; VAUX = 3.3V; (Note 2) 8(min.) KV L-H Propagation Delay@ CL = 50pF; VCC = 5V; RL = 500W; (Note 3) 7(typ.) 15(max.) ns H-L Propagation Delay @ CL = 50pF; VCC = 5V; RL = 500W.; (Note 3) 7(typ.) 15(max.) ns Output Rise and Fall Time @ CL = 50pF; VCC = 5V; RL = 500W .; (Note 3) 7(typ.) ns Note 1: These parameters apply only to the HSYNC and VSYNC signals. Note.2 Per the IEC-1000-4-2 ESD Standard, Level 4 contact discharge method. VRGB and VCC must each be bypassed to GND with a 0.2F, low inductance, chip ceramic capacitor at the appropriate supply pin. This parameter is guaranteed by design and device characterization. ESD pulse is applied between the applicable pins and GND. ESD pulse can be positive or negative with respect to GND. Applicable pins are: R, G, B, HSYNC_OUT, VSYNC_OUT, DDC_CLK and DDC_DATA. The HSYNC and VSYNC inputs are ESD protected to the industry standard 2KV per the Human Body model (MIL-STD-883, Method 3015). Note 3.Applicable to the SYNC buffers only. Input signals swing between 0V and 3.0V, with rise and fall times =5nS. Guaranteed by correlation to buffer output drive currents. Note 4 Measured at 1MHz. R/G/B inputs biased at 1.65V, with VRGB = 3.3V. DDC_CLK and DDC_DATA biased at 2.5V, with VCC = 5V. HSYNC and VSYNC inputs biased at VAUX or GND, with VAUX = 3.3V and VCC = 5V. These parameters are guaranteed by design and characterization. PIN DESCRIPTION LEAD NAME 1 HSYNC_OUT 2 HSYNC 3, 11 GNDD 4 VRGB 5 B 6 G 7 R 8 GNDA 9, 16 VCC 10 DCC_DATA 12 DCC_CLOCK 13 VAUX 14 VSYNC 15 VSYNC_OUT GENERAL DIE INFORMATION Substrate Thickness (mils) Die size (mils) Bonding pads Backside metal SiO2 / Silicon 102 90 x 60 3 4x4 mils, 3mm thick, 99.99% electroplated gold with a TiW barrier Au/Si compatible with eutectic and conductive epoxy die attach. All Semiconwell products are available in die form for chip and wire hybrid circuits and multi chip modules applications. Typical delivery for standard die products is 3-4 weeks ARO. For Chip Scale Packaged (CSP) devices consult factory for an update on availability of certain products. DIODES RESISTORS CAPACITORS Diodes offers basic ESD protection, with low forward voltage and low power dissipation. Diodes are small physically resulting low junction capacitance and low loading capacitance. Resistive material is ultra stable TaN with low TCR <75ppm/C typical. For Rsq<10W/sq and Rsq>500W/sq, the resistive material is proprietary. Power rating/resistor max 100mW for R<1KW and 25mW for R>1KW. Standard tolerance is 5%. Silicon nitride dielectric, MNOS capacitors exhibit high stability, low temperature coefficients, low leakage <10nA and high BV>50V. DIE LAYOUT PACKAGE PIN OUT Vin=3,4,5,6,11,12,13,14 Vss=die backside Vss=1,8,9,16 Vdd=2,7,10,15 STANDARD PRODUCTS ORDERING INFORMATION SOIC-16 QSOP-16 TSSOP-16 BARE DIE-16 SWVGA105-16SC SWVGA105-16QS SWVGA105-16TS SWVGA105-16BD SW PART # QUANTITY SOIC-16 U/P($) QSOP-16 U/P($) TSSOP-16 U/P($) BARE DIE U/P($) SWVGA105 5,000pc -16SO -16QS -16TS -16BD SWVGA105 10,000pc -16SO -16QS -16TS -16BD For products sold as bare tested die or known good die KGD, minimum order is 5000pc. Dice are 100% functional tested, visual inspected and shipped in antistatic waffle packs. For special die level KGD requirements, different packaging or custom configurations, contact sw_sales@semiconwell.com Delivery for packaged RCD standard products is 6-8 weeks ARO. Certain items may be available from stock. For standard products available from stock, there is a minimum line item order of $250.0. Inventory is periodically updated. For 2500pc or larger orders, all surface mount packaged devices are shipped in tape on reel (T/R). For smaller quantities, it may vary. Samples are available only for customers that have issued firm orders pending qualification of product in a particular application. On line Orders have to be verified, accepted and acknowledged by Semiconwell sales department in writing before, becoming non cancelable binding contracts. Semiconwell guarantees continuous supply and availability of any of it's standard products provided minimum order quantities are met. SEMICONWELL has made every effort to have this information as accurate as possible. However, no responsibility is assumed by SEMICONWELL for its use, nor for any infringements of rights of third parties which may result from its use. SEMICONWELL reserves the right to revise the content or modify its product line without prior notice. SEMICONWELL products are not authorized for and should not be used within support systems which are intended for surgical implants into the body, to support or sustain life, in aircraft, space equipment, submarine, or nuclear facility applications without the specific written consent.

 
 
SEMICONWELL
Integrated Passive Networks
  PRELIMINARY
VGA PORT ESD PROTECTED TERMINATION

SWVGA-105
 
 

FEATURES
APPLICATIONS
SCHEMATIC
7 channels of ESD protection designed to meet IEC-1000-4-2 Level-4 ESD requirements (8KV contact discharge)
Very low loading capacitance from ESD protection diodes, < 5pF typical
TTL to CMOS level-translating buffers for the HSYNC and VSYNC lines
Three independent supply pins to facilitate operation with sub-micron Graphics Controller ICs
High impedance pull-ups (50kW to nominal VAUX for HSYNC & VSYNC inputs
Pull-up resistors (1.8KW nominal to VCC ) for DDC_CLK and DDC_DATA lines
ESD protection for VGA (video) port in PCs and notebooks.
schematic

SHORT PRODUCT APPLICATION NOTE
The SWVGA-105 incorporates 7 channels of ESD protection for signal lines commonly found in a VGA port for PCs. ESD protection is implemented with current steering diodes designed to safely handle the high peak surge currents associated with the IEC-1000-4-2 Level-4 ESD Protection Standard (8KV contact discharge). When the channels are subjected to an electrostatic discharge, the ESD current pulse is diverted via the protection diodes into the positive supply rails or ground where they may be safely dissipated. The upper ESD diodes for the R, G & B channels are connected to a separate supply rail (VRGB ) to facilitate interfacing to graphics controller ICs with low voltage supplies. The remaining channels are connected to the main 5V rail (VCC ). The lower diodes for the R, G & B channels are also connected to a dedicated ground pin (GNDA) to minimize crosstalk due to common ground impedance. Two non-inverting buffers are also included in this IC for buffering the HSYNC and VSYNC signals from the graphics controller IC. These buffers will accept TTL input levels and convert them to CMOS output levels that swing between GND and VCC . These drivers have a nominal 60W output impedance to match the characteristic impedance of the HSYNC and VSYNC lines of the video cables typically used.The inputs of these drivers also have high impedance pull-ups (50KW nom.) pulling up to the V rail. In addition, the DDC_CLOCK and DDC_DATA channels have 1.8KW .pull-up resistors pulling these inputs up to the main 5V (VCC ) rail.

SEMICONDUCTOR-THIN FILM MANUFACTURING PROCESS DESCRIPTION
Integrated passive networks are manufactured using advanced thin film technologies including ultra -stable and self passivating Tantalum Nitride resistors, gold interconnect metallization and reliable MNOS capacitors to achieve excellent uniformity, performance and reliability. Thin film resistor technology is the preferred solution for all applications that require low noise, long term stability and excellent performance at very high frequencies. Semiconwell employs proprietary thin film technologies for deposition of a wide range of sheet resistance films from 1W/sq to 10,000 W/sq. All Semiconwell's products are available in die form and as KGD, known good die and are ideal for high reliability hybrid and multi chip module applications. Besides thin film resistors, Semiconwell integrates capacitors, Schottky diodes, Zener diodes and transistors. Integrated passive and active networks are manufactured using Semiconwell's in house high reliability semiconductor manufacturing processes. All semiconductor devices employ precision doping via ion implantation, silicon nitride junction passivation, platinum silicided contacts and gold interconnect metallization for best performance and reliability. MNOS capacitors and Tantalum Nitride resistors are easily integrated with Schottky diodes to provide complete standard and custom RCD solutions. In die form, these products are ideal for hybrid and multi chip module applications. In packaged form, these products are the best solution where space and weight are a concern.

ABSOLUTE MAXIMUM RATINGS
Reverse voltage VR Continuous IF IFRM for tw<100ms Max Power dissipation
7V 100mA 200 mA (20%duty cycle) 100mW@70°C/channel

Stresses beyond listed absolute maximum ratings may cause permanent damage to the device.

ABSOLUTE MAXIMUM RATINGS
PARAMETER VALUE UNITS
VCC Supply Voltage GND-0.5, 6.0 V
VRGB Supply Voltage GND-0.5, 6.0 V
VAUX Supply Voltage GND-0.5, 6.0 V
Diode Forward Current (only one diode conducting at a time) 20 mA
DC Voltage at Inputs ,R, G, B GND -0.5, VRGB +0.5 V
DC Voltage at Inputs ,HSYNC, VSYNC GND -0.5, VAUX +0.5 V
DC Voltage at Inputs ,DDC_CLK, DDC_DATA GND -0.5, VCC +0.5 V
Storage Temperature -40 to 150 °C
Operating Ambient Temperature 0 to 70 °C
Package Power Dissipation 0.75 W
RECOMMENDED OPERATING CONDITIONS
PARAMETER VALUE UNITS
Main Supply Voltage
4.5(min.)  5.5(max.)
V
RGB Supply Voltage
1.7(min.)  3.7(max.)
V
Auxiliary Supply Voltage
2.9(min.)  3.7(max.)
V
Logic High Input Voltage (Note 1)
2.0(min.)
V
Logic Low Input Voltage (Note 1)
0.8(max.)
V
Input Voltage ,RGB
0(min.)  VRGB(max.)
V
Input Voltage ,HSYNC, VSYNC
0(min.)  VAUX(max.)
V
Input Voltage ,DDC_CLK, DDC_DATA
0(min.)  VCC(max.)
V
High Level Output Current (Note 1)
-8(max.)
mA
Low Level Output Current (Note 1)
8(max.)
mA
Operating Free-Air Temperature
0(min.)  70(max.)
°C
ELECTRICAL CHARACTERISTICS
PARAMETER VALUE UNITS
Diode Forward Voltage@IF = 10mA 1(max.) V
Logic High Output Voltage@IOH = -4mA, VCC = 4.5V 4(min.) V
Logic Low Output Voltage@IOL = 4mA, VCC = 4.5V 0.4(max.) V
Input Current,R, G, B pins; VRGB = 3.63V; VIN = VRGB or GND ±1 mA
Input Current,HSYNC, VSYNC pins; VAUX = 3.63V; VIN = VAUX ±1 mA
Input Current,HSYNC, VSYNC pins; VAUX = 3.63V; VIN = GND -30(min.)  -72.5(typ.)  -95(max.) mA
VCC Supply Current @ V CC = 5.5V; VAUX = VRGB = 2.97V;All inputs and outputs floating 35(typ.)  100(max.) mA
VRGB Supply Current @ R, G, B pins at VCC or GND;All other input and output floating 10(max.) mA
Input Capacitance,R,G, B (Note 4) 5(typ.) pF
Input Capacitance, HSYNC, VSYNC (Note 4) 10(typ.) pF
Input Capacitance, DDC_DATA, DDC_CLK (Note 4) 5(typ.) pF
Pull-up Resistance DDC_DATA, DDC_CLK 1.62(min.)  1.8(typ.)  1.98(max.) kW
ESD Withstand Voltage, @ VCC = 5V; VRGB = 3.3V; VAUX = 3.3V; (Note 2) ±8(min.) KV
L-H Propagation Delay@ CL = 50pF; VCC = 5V; RL = 500W; (Note 3) 7(typ.)  15(max.) ns
H-L Propagation Delay @ CL = 50pF; VCC = 5V; RL = 500W.; (Note 3) 7(typ.)  15(max.) ns
Output Rise and Fall Time @ CL = 50pF; VCC = 5V; RL = 500W .; (Note 3) 7(typ.) ns
 
Note 1: These parameters apply only to the HSYNC and VSYNC signals.
Note.2 Per the IEC-1000-4-2 ESD Standard, Level 4 contact discharge method. VRGB and VCC must each be bypassed to GND with a 0.2µF, low inductance, chip ceramic capacitor at the appropriate supply pin. This parameter is guaranteed by design and device characterization. ESD pulse is applied between the applicable pins and GND. ESD pulse can be positive or negative with respect to GND. Applicable pins are: R, G, B, HSYNC_OUT, VSYNC_OUT, DDC_CLK and DDC_DATA. The HSYNC and VSYNC inputs are ESD protected to the industry standard 2KV per the Human Body model (MIL-STD-883, Method 3015).
Note 3.Applicable to the SYNC buffers only. Input signals swing between 0V and 3.0V, with rise and fall times =5nS. Guaranteed by correlation to buffer output drive currents.
Note 4 Measured at 1MHz. R/G/B inputs biased at 1.65V, with VRGB = 3.3V. DDC_CLK and DDC_DATA biased at 2.5V, with VCC = 5V. HSYNC and VSYNC inputs biased at VAUX or GND, with VAUX = 3.3V and VCC = 5V. These parameters are guaranteed by design and characterization.

PIN DESCRIPTION
LEAD NAME
1 HSYNC_OUT
2 HSYNC
3, 11 GNDD
4 VRGB
5 B
6 G
7 R
8 GNDA
9, 16 VCC
10 DCC_DATA
12 DCC_CLOCK
13 VAUX
14 VSYNC
15 VSYNC_OUT

GENERAL DIE INFORMATION
Substrate Thickness (mils) Die size (mils) Bonding pads Backside metal
SiO2 / Silicon 10±2 90 x 60 ±3 4x4 mils, 3mm thick, 99.99% electroplated gold with a TiW barrier Au/Si compatible with eutectic and conductive epoxy die attach.
All Semiconwell products are available in die form for chip and wire hybrid circuits and multi chip modules applications. Typical delivery for standard die products is 3-4 weeks ARO. For Chip Scale Packaged (CSP) devices consult factory for an update on availability of certain products.

DIODES RESISTORS CAPACITORS
Diodes offers basic ESD protection, with low forward voltage and low power dissipation. Diodes are small physically resulting low junction capacitance and low loading capacitance. Resistive material is ultra stable TaN with low TCR <75ppm/°C typical. For Rsq<10W/sq and Rsq>500W/sq, the resistive material is proprietary. Power rating/resistor max 100mW for R<1KW and 25mW for R>1KW. Standard tolerance is ±5%. Silicon nitride dielectric, MNOS capacitors exhibit high stability, low temperature coefficients, low leakage <10nA and high BV>50V.

DIE LAYOUT PACKAGE PIN OUT
layout / design pending schematic
Vin=3,4,5,6,11,12,13,14
Vss=die backside
Vss=1,8,9,16
Vdd=2,7,10,15

STANDARD PRODUCTS ORDERING INFORMATION

SOIC-16 QSOP-16 TSSOP-16 BARE DIE-16
SWVGA105-16SC SWVGA105-16QS SWVGA105-16TS SWVGA105-16BD

SW PART # QUANTITY SOIC-16 U/P($) QSOP-16 U/P($) TSSOP-16 U/P($) BARE DIE U/P($)
SWVGA105   5,000pc -16SO   -16QS   -16TS   -16BD  
SWVGA105 10,000pc -16SO   -16QS   -16TS   -16BD  
For products sold as bare tested die or known good die KGD, minimum order is 5000pc. Dice are 100% functional tested, visual inspected and shipped in antistatic waffle packs. For special die level KGD requirements, different packaging or custom configurations, contact sw_sales@semiconwell.com

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Delivery for packaged RCD standard products is 6-8 weeks ARO. Certain items may be available from stock. For standard products available from stock, there is a minimum line item order of $250.0. Inventory is periodically updated. For 2500pc or larger orders, all surface mount packaged devices are shipped in tape on reel (T/R). For smaller quantities, it may vary. Samples are available only for customers that have issued firm orders pending qualification of product in a particular application. On line Orders have to be verified, accepted and acknowledged by Semiconwell sales department in writing before, becoming non cancelable binding contracts.

Semiconwell guarantees continuous supply and availability of any of it's standard products provided minimum order quantities are met.

SEMICONWELL has made every effort to have this information as accurate as possible. However, no responsibility is assumed by SEMICONWELL for its use, nor for any infringements of rights of third parties which may result from its use. SEMICONWELL reserves the right to revise the content or modify its product line without prior notice. SEMICONWELL products are not authorized for and should not be used within support systems which are intended for surgical implants into the body, to support or sustain life, in aircraft, space equipment, submarine, or nuclear facility applications without the specific written consent.

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